november 1992 revised january 1999 74abt543 octal registered transceiver with 3-state outputs ? 1999 fairchild semiconductor corporation ds011508.prf www.fairchildsemi.com 74abt543 octal registered transceiver with 3-state outputs general description the abt543 octal transceiver contains two sets of d-type latches for temporary storage of data flowing in either direction. separate latch enable and output enable inputs are provided for each register to permit independent con- trol of inputting and outputting in either direction of data flow. features n back-to-back registers for storage n bidirectional data path n a and b outputs have current sourcing capability of 32 ma and current sinking capability of 64 ma n separate controls for data flow in each direction n guaranteed output skew n guaranteed multiple output switching specifications n output switching specified for both 50 pf and 250 pf loads n guaranteed simultaneous switching noise level and dynamic threshold performance n guaranteed latchup protection n high impedance glitch free bus loading during entire power up and power down cycle n nondestructive hot insertion capability ordering code: device also available in tape and reel. specify by appending suffix letter x to the ordering code. connection diagram pin assignment for soic, ssop and tssop pin descriptions order number package number package description 74abt543csc m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide body 74abt543cmsa msa24 24-lead shrink small outline package (ssop), eiaj type ii, 5.3mm wide 74abt543cmtc mtc24 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description oeab , oeba output enable inputs leab , leba latch enable inputs ceab , ceba chip enable inputs a 0 Ca 7 side a inputs or 3-state outputs b 0 Cb 7 side b inputs or 3-state outputs
www.fairchildsemi.com 2 74abt543 functional description the abt543 contains two sets of d-type latches, with sep- arate input and output controls for each. for data flow from a to b, for example, the a to b enable (ceab ) input must be low in order to enter data from the a port or take data from the b port as indicated in the data i/o control table. with ceab low, a low signal on (leab ) input makes the a to b latches transparent; a subsequent low to high transi- tion of the leab line puts the a latches in the storage mode and their outputs no longer change with the a inputs. with ceab and oeab both low, the b output buffers are active and reflect the data present on the output of the a latches. control of data flow from b to a is similar, but using the ceba , leba and oeba . data i/o control table h = high voltage level l = low voltage level x = immaterial logic diagram inputs latch status output buffers ceab leab oeab h x x latched high z x h x latched l l x transparent x x h high z l x l driving
3 www.fairchildsemi.com 74abt543 absolute maximum ratings (note 1) recommended operating conditions note 1: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. functional operation under these conditions is not implied. note 2: either voltage limit or current limit is sufficient to protect inputs. dc electrical characteristics note 3: guaranteed but not tested. note 4: for 8-bit toggling. i ccd < 1.4 ma/mhz. note 5: guaranteed, but not tested. storage temperature - 65 c to + 150 c ambient temperature under bias - 55 c to + 125 c junction temperature under bias - 55 c to + 150 c v cc pin potential to ground pin - 0.5v to + 7.0v input voltage (note 2) - 0.5v to + 7.0v input current (note 2) - 30 ma to + 5.0 ma voltage applied to any output in the disable or power-off state - 0.5v to + 5.5v in the high state - 0.5v to v cc current applied to output in low state (max) twice the rated i ol (ma) dc latchup source current - 500 ma over voltage latchup (i/o) 10v free air ambient temperature - 40 c to + 85 c supply voltage + 4.5v to + 5.5v minimum input edge rate ( d v/ d t) data input 50 mv/ns enable input 20 mv/ns clock input 100 mv/ns symbol parameter min typ max units v cc conditions v ih input high voltage 2.0 v recognized high signal v il input low voltage 0.8 v recognized low signal v cd input clamp diode voltage - 1.2 v i in = - 18 ma (non i/o pins) v oh output high voltage 2.5 i oh = - 3 ma, (a n , b n ) 2.0 i oh = - 32 ma, (a n , b n ) v ol output low voltage 0.55 v min i ol = 64 ma, (a n , b n ) v id input leakage test 4.75 v 0.0 i id = 1.9 m a, (non-i/o pins) all other pins grounded i ih input high current 1 m amaxv in = 2.7v (non-i/o pins) (note 3) 1v in = v cc (non-i/o pins) i bvi input high current breakdown test 7 m amaxv in = 7.0v (non-i/o pins) i bvit input high current 100 m amaxv in = 5.5v (a n , b n ) breakdown test (i/o) i il input low current - 1 m amaxv in = 0.5v (non-i/o pins) (note 3) - 1v in = 0.0v (non-i/o pins) i ih + i ozh output leakage current 10 m a 0vC5.5v v out = 2.7v (a n , b n ); oeab or ceab = 2v i il + i ozl output leakage current - 10 m a 0vC5.5v v out = 0.5v (a n , b n ); oeab or ceab = 2v i os output short-circuit current - 100 - 275 ma max v out = 0v (a n , b n ) i cex output high leakage current 50 m amaxv out = v cc (a n , b n ) i zz bus drainage test 100 m a0.0vv out = 5.5v (a n , b n ); all others gnd i cclh power supply current 50 m a max all outputs high i ccl power supply current 30 ma max all outputs low i ccz power supply current 50 m a max outputs 3-state all others at v cc or gnd i cct additional i cc /input 2.5 ma max v i = v cc - 2.1v all others at v cc or gnd i ccd dynamic i cc no load outputs open, ceab (note 5) 0.18 ma/mhz max and oeab = gnd, ceba = v cc , one bit toggling, 50% duty cycle, (note 4)
www.fairchildsemi.com 4 74abt543 dc electrical characteristics (soic package) note 6: max number of outputs defined as (n). n - 1 data inputs are driven 0v to 3v. one output at low. guaranteed, but not tested. note 7: max number of outputs defined as (n). n - 1 data inputs are driven 0v to 3v. one output high. guaranteed, but not tested. note 8: max number of data inputs (n) switching. n - 1 inputs switching 0v to 3v. input-under-test switching: 3v to threshold (v ild ), 0v to threshold (v ihd ). guaranteed, but not tested. ac electrical characteristics (soic and ssop packages) ac operating requirements (soic and ssop packages) conditions symbol parameter min typ max units v cc c l = 50 pf, r l = 500 w v olp quiet output maximum dynamic v ol 0.7 1.0 v 5.0 t a = 25 c (note 6) v olv quiet output minimum dynamic v ol - 1.2 - 0.8 v 5.0 t a = 25 c (note 6) v ohv minimum high level dynamic output voltage 2.5 3.0 v 5.0 t a = 25 c (note 7) v ihd minimum high level dynamic input voltage 2.0 1.7 v 5.0 t a = 25 c (note 8) v ild maximum low level dynamic input voltage 0.7 0.9 v 5.0 t a = 25 c (note 8) symbol parameter t a = + 25 ct a = - 40 c to + 85 c units v cc = + 5.0v v cc = 4.5vC5.5v c l = 50 pf c l = 50 pf min typ max min max t plh propagation delay 1.5 3.1 4.8 1.5 4.8 ns t phl a n to b n or b n to a n 1.5 4.8 1.5 4.8 t plh propagation delay t phl leab to b n , leba to a n 1.6 3.4 5.3 1.6 5.3 ns oeba or oeab to a n or b n 1.6 5.3 1.6 5.3 t pzh enable time t pzl leab to b n , leba to a n 1.5 3.6 5.8 1.5 5.8 ns oeba or oeab to a n or b n 1.5 5.8 1.5 5.8 t phz disable time 2.0 4.0 6.5 2.0 6.5 ns t plz ceba or ceab to a n or b n 2.0 6.5 2.0 6.5 symbol parameter t a = + 25 ct a = - 40 c to + 85 c units v cc = + 5.0v v cc = 4.5vC5.5v c l = 50 pf c l = 50 pf minmaxminmax t s (h) setup time, high or low 1.5 1.5 ns t s (l) a n or b n to leba or leab 1.5 1.5 t h (h) hold time, high or low 1.0 1.0 ns t h (l) a n or b n to leba or leab 1.0 1.0 t s (h) setup time, high or low 1.5 1.5 ns t s (l) a n or b n to ceab or ceba 1.5 1.5 t h (h) hold time, high or low 1.3 1.3 ns t h (l) a n or b n to ceab or ceba 1.3 1.3 t w (l) pulse width, low 3.0 3.0 ns
5 www.fairchildsemi.com 74abt543 extended ac electrical characteristics (soic package) note 9: this specification is guaranteed but not tested. the limits apply to propagation delays for all paths described switching in ph ase (i.e., all low-to- high, high-to-low, etc.). note 10: this specification is guaranteed but not tested. the limits represent propagation delay with 250pf load capacitors in place of the 50 pf load capac- itors in the standard ac load. this specification pertains to single output switching only. note 11: this specification is guaranteed but not tested. the limits represent propagation delays for all paths described switching in p hase (i.e., all low-to- high, high-to-low, etc.) with 250 pf load capacitors in place of the 50 pf load capacitors in the standard ac load. note 12: the 3-state delay times are dominated by the rc network (500 w , 250 pf) on the output and has been excluded from the datasheet skew (soic package) note 13: this specification is guaranteed but not tested. the limits apply to propagation delays for all paths described switching in ph ase (i.e., all low-to- high, high-to-low, etc.). note 14: this specification is guaranteed but not tested. the limits represent propagation delays with 250 pf load capacitors in place of the 50 pf load capacitors in the standard ac load. note 15: skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of t he same device. the specification applies to any outputs switching high-to-low (t oshl ), low-to-high (t oslh ), or any combination switching low-to-high and/or high- to-low (t ost ). this specification is guaranteed but not tested. note 16: this describes the difference between the delay of the low-to-high and the high-to-low transition on the same pin. it is measur ed across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. this specification is guaranteed but not tested. note 17: propagation delay variation for a given set of conditions (i.e., temperature and v cc ) from device to device. this specification is guaranteed but not tested. symbol parameter t a = - 40 c to + 85 ct a = - 40 c to + 85 ct a = - 40 c to + 85 c units v cc = 4.5vC5.5v v cc = 4.5vC5.5v v cc = 4.5vC5.5v c l = 50 pf c l = 250 pf c l = 250 pf 8 outputs switching 1 output switching 8 outputs switching (note 9) (note 10) (note 11) min typ max min max min max f toggle max toggle frequency 100 mhz t plh propagation delay 1.5 6.2 2.0 7.5 2.5 10.0 ns t phl a n to b n or b n to a n 1.5 6.2 2.0 7.5 2.5 10.0 t plh propagation delay 1.5 6.5 2.0 8.0 2.5 10.5 ns t phl leab to b n , leba to a n 1.5 6.5 2.0 8.0 2.5 10.5 t pzh output enable time t pzl oeba or oeab to a n or b n 1.5 7.5 2.0 8.5 2.5 11.0 ns ceba or ceab to a n or b n 1.5 7.5 2.0 8.5 2.5 11.0 t phz output disable time t plz oeba or oeab to a n or b n 1.5 8.5 (note 12) (note 12) ns ceba or ceab to a n or b n 1.5 8.5 symbol parameter t a = - 40 c to + 85 ct a = - 40 c to + 85 c units v cc = 4.5vC5.5v v cc = 4.5vC5.5v c l = 50 pf c l = 250 pf 8 outputs switching 8 outputs switching (note 13) (note 14) max max t oshl pin to pin skew 1.0 2.0 ns (note 15) hl transitions t oslh pin to pin skew 1.3 2.0 ns (note 15) lh transitions t ps duty cycle 2.0 4.0 ns (note 16) lhChl skew t ost pin to pin skew 2.0 4.0 ns (note 15) lh/hl transitions t pv device to device skew 2.5 4.5 ns (note 17) lh/hl transitions
www.fairchildsemi.com 6 74abt543 capacitance note 18: c i/o is measured at frequency, f = 1 mhz, per mlt-std-883b, method 3012. ac loading *includes jig and probe capacitance figure 1. standard ac test load figure 2. v m = 1.5v input pulse requirements figure 3. test input signal requirements ac waveforms figure 4. propagation delay waveforms for inverting and non-inverting functions figure 5. propagation delay, pulse width waveforms figure 6. 3-state output high and low enable and disable times figure 7. setup time, hold time and recovery time waveforms symbol parameter typ units conditions: t a = 25 c c in input capacitance 5.0 pf v cc = 0v (non i/o pins) c i/o (note 18) output capacitance 11.0 pf v cc = 5.0v (a n , b n ) amplitude rep. rate t w t r t f 3v 1 mhz 500 ns 2.5 ns 2.5 ns
7 www.fairchildsemi.com 74abt543 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide body package number m24b 24-lead shrink small outline package (ssop), eiaj type ii, 5.3mm wide package number msa24
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. 74abt543 octal registered transceiver with 3-state outputs life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc24
|
